Voltage multipliers are commonly used to increase the voltage of a supply source in order to provide the higher voltages needed to operate circuit elements. One type of voltage multiplier is called a charge pump and is commonly used in memory systems to provide the voltages needed for accessing, programming or erasing memory cells.
For example, in the field of dynamic random access memory (DRAM) a charge pump circuit is typically used to generate a voltage which is used to enable a memory cell access transistor. A DRAM cell typically consists of a cell storage capacitor that stores a data bit as a voltage level and an n-channel field effect transistor (NFET) as an access transistor. A typical DRAM cell is depicted in FIG. 1. The memory cell is written by driving a potential of either 0 volts or Vdd volts onto the cell capacitor C through the access transistor Q. Vdd is the primary externally-provided power supply voltage, which is typically 2.5 or 3.3 volts. In order to fully and quickly drive the voltage across the cell capacitor C to Vdd when writing a high voltage to the cell, it is necessary to raise the potential on the gate of the access transistor Q to a value Vpp that is several volts above Vdd. This potential Vpp, which is higher than the externally-supplied power supply voltage Vdd, is typically provided by a charge pump circuit. Vpp must be several volts above Vdd in order to overcome the body-effect enhanced threshold voltage of the access transistor Q.
For a variety of reasons, it is desirable to generate the Vpp potential internally to the DRAM device rather than providing it to the DRAM from an external power supply unit. The traditional means of generating Vpp within a DRAM is through the use of a single-stage, two-phase charge pump power supply circuit, which can generate potentials as high as twice Vdd. For example, for a Vdd of 2.5 volts, a potential of approximately 5.0 volts can be generated, although the steady-state Vpp value is usually regulated to a level around 3.5 V to 4.0 V through an associated regulator circuit. A typical single-stage, two-phase charge pump is shown in FIG. 2A. FIG. 2B illustrates four inverting stages and the corresponding clocks signals which are used to drive the charge pump circuit shown in FIG. 2A.
Semiconductor fabrication processes have advanced to include smaller transistor feature sizes and shorter transistor gate lengths. As such, the externally-supplied power supply voltage Vdd has been lowered proportionately to avoid damage to standard logic transistors. This reduction in Vdd has not been accompanied by a similar reduction in DRAM access transistor threshold voltage. As a result, the traditional single-stage, two-phase charge pump can no longer provide the necessary Vpp level needed for robust DRAM operation.
The requirement for voltages of more than twice Vdd has been previously faced in the field of non-volatile memory, specifically with devices such as flash EEPROM. A commonly used high voltage supply circuit for such applications is a four-stage, four-phase charge pump employing boosted gate transistors, as shown in FIG. 3A.
FIG. 3A is a schematic diagram of a prior art four-stage, four-phase bootstrap charge pump circuit 10. Charge pump circuit 10 includes four-stages consisting of n-type field effect transistors (NFETs) and capacitors. The first stage includes NFET transistors 23 and 19 and capacitors 11 and 15, the second stage includes NFET transistors 24 and 20 and capacitors 12 and 16, the third stage includes NFET transistors 25 and 21 and capacitors 13 and 17, and the fourth stage includes NFET transistors 26 and 22 and capacitors 14 and 18, respectively. The four stages are connected in series between an input supply voltage Vdd and an output terminal Vout. Clock signal PHI1 is provided to capacitors 15 and 17 while clock signal PHI2 is provided to capacitors 16 and 18. Furthermore, boosting clock signals B1 and B2 are provided to capacitors 11, 13 and 12, 14, respectively.
FIG. 3B illustrates the relative timing of the clock signals PHI1, PHI2, B1 and B2, which are used to drive the pump circuit of FIG. 3A. Clock signals PHI1 and PHI2 are driven by opposite phases of a system clock signal CLK. It should be noted that the relative timing of these clock signals must be carefully overlapped in order to provide the appropriate operation of the charge pump as will be described below.
The operation of charge pump circuit 10 will now be discussed with reference to FIG. 3A and FIG. 3B and specifically with reference to the second pump stage. It is initially assumed that at some time prior to the timing intervals shown in FIG. 3B, boosting clock signal B1 was high and, as a result of the boosting action of capacitor 11, pass transistor 23 was turned on fully, thereby passing a voltage Vdd at the output of the first stage, i.e. the upper plate of capacitor 15. The initial conditions shown in FIG. 3B begin with clock signal PHI2 being at a high level while clock signals PHI1, B1 and B2 are at a low level. Since PHI2 is high, transistor 20 is turned on fully due to the boosting action of capacitor 16, and since transistor 20 is on turned on fully, transistor 24 exhibits the same voltage at its gate and drain, i.e. the voltage Vdd stored on capacitor 15. At time t1, clock signal PHI1 goes high, boosting the upper plate of capacitor 15 to a voltage level equal to 2 Vdd. Since PHI2 is still high at time t1, transistor 20 is still turned on and, as a result, transistor 20 passes the boosted gate voltage of 2 Vdd on to capacitor 12 at the gate terminal of transistor 24. When PHI2 then goes low at time t2, transistor 20 is turned off, isolating the gate of transistor 24 and leaving capacitor 12 charged to a voltage level equal to 2 Vdd. At time t3, boosting clock signal B2 goes high causing the voltage at the gate terminal of transistor 24 to be boosted to a voltage level equal to 3 Vdd, thereby fully turning on transistor 24. Transistor 24 thus passes the full voltage of 2 Vdd which is stored on capacitor 15 on to the next stage, i.e. the upper plate of capacitor 16, without any threshold drop across transistor 24. At time t4, boosting clock signal B2 goes low and transistor 24 begins to turn off, which isolates the boosted node on capacitor 16. Subsequently, at time t5, PHI2 rises, turning on transistor 20 and thereby discharging the gate terminal of transistor 24 to the voltage level at the drain terminal of transistor 24. At time t6, when PHI1 goes low, transistor 24 remains off while transistor 20 remains on.
The operation of charge pump circuit 10 has been discussed with emphasis on the second stage of the charge pump and will now be discussed with respect to the entire charge pump. The following sequence occurs within each pump stage: the bootstrapping transistor of a particular stage (transistor 19 in stage 1, transistor 20 in stage 2, transistor 21 in stage 3, and transistor 22 in stage 4) is turned on fully. The bootstrapping transistor thus precharges the gate terminal of the pass transistor for that particular stage (transistor 23 for stage 1, transistor 24 for stage 2, transistor 25 for stage 3, and transistor 27 for stage 4) to a voltage equal to the pass transistor's drain voltage. Subsequently, the bootstrap transistor (19, 20, 21, or 22) is turned off and the gate terminal of the pass transistor (23, 24, 25 or 26) is isolated and remains charged. Shortly thereafter, a boosting clock signal (B1 or B2) is delivered through a boosting capacitor (11, 12, 13 or 14) to the gate terminal of the pass transistor (23, 24, 25 or 26), thereby boosting the gate and allowing the pass transistor to pass the full voltage at its drain with no threshold voltage drop. Finally, the main pumping clock signal for that particular stage (PHI1 for stages 1 and 3, and PHI2 for stages 2 and 4) boosts the source voltage on the pass transistor (23, 24, 25 or 26), thereby increasing the output of that stage by an additional voltage level Vdd and providing this increased voltage to the next stage. It should be noted that due to the main pumping clock signals PHI1 and PHI2, stages 1 and 3 of the charge pump operate in tandem, and stages 2 and 4 operate in tandem, but stages 1 and 3 operate on the opposite phase compared to stages 2 and 4. This process continues until sufficient voltage is generated on the output Vout, as detected by a level detector within a regulator (not shown in FIG. 3A). Typically, when the appropriate level has been reached, the clock signals used to drive the pump will be disabled until the level detector detects a drop in Vout which is below a predetermined level. At this point, the clock signals will once again be activated.
The third and fourth stages of charge pump circuit 10 therefore operate in the same manner as the first and second stages. The second stage passes onto the third stage a voltage equal to three times the input supply voltage Vdd, and the third stage passes on to the fourth stage a voltage equal to four times the input supply voltage Vdd. The fourth stage drives output transistor 27, which is configured to finction as a diode. Output transistor 27 is in a conductive state only when clock signal PHI2 goes high, which corresponds to the falling edge of input clock signal CLK. Therefore, the output terminal Vout is driven only on the falling edge of input clock signal CLK. The output terminal provides a voltage Vout that equals four times the input supply voltage Vdd.
The four-stage, four-phasc charge pump design shown in FIG. 3A has several drawbacks that make it unsuitable for use as a Vpp supply circuit for low voltage DRAM applications. Four pump stages are not required to generate Ithe necessary voltage level for Vpp in a DRAM application. The four-stage, fourphase charge pump also contributes to a larger circuit size and greater energy loss at the higher peak and average current levels required by a DRAM. Further, the use of boosted gate transistors could hinder the ability of the power supply to adapt to rapid increases in Vpp current demand under certain circumstances, such as when a DRAM exits a power down state. In addition, the four individual clock phases required to drive the charge pump shown in FIG. 3A need to be very precisely generated, ensuring the appropriate overlap times required to accomplish the boosting operations. If the clock timings are not accurately implemented, charge leakage from an up-stream stage may occur to a down-stream phase, thereby significantly reducing the efficiency of the charge pump.
An enhancement of the four-stage four-phase charge pump is shown in FIG. 4A. In this approach, an n-channel FET N1 is used to equalize the charge pump clock inputs X1 and X2. This allows charge sharing to occur during the non-overlap period between clock phases as shown in FIG. 4B. By equalizing the clock inputs in this fashion, the amount of power used by the tristate buffers B1 and B2 (comprised of transistors P1, N11 and P2, N12, respectively) which generate the clock signals is reduced, thereby increasing the conversion efficiency of the charge pump circuit. It should be noted that in the implementation described with reference to FIG. 4A and FIG. 4B, clock signals X1 and X2, which are equalized by transistor N1 during the non-overlapping period, are also driven by tri-state buffers B1 and B2. As a result there is a potential overlap in the operation of equalization transistor N1 and the tri-state buffer transistors P1, N11 and P2, N12. Forexample, considering the initial conditions shown in FIG. 4B, signal Y1 is logic low, signal Y2 is logic high and as a result, transistor P2 of buffer B2 is on and transistor N11 of buffer B1 is on, resulting in signal X1 being logic low and signal X2 being logic high. When Y2 begins to transition from logic high to logic low, transistor N11 will begin to turn off, NOR gate G1, which generates the EQ pulse, will begin to turn on and the inverter driving transistor P2 will begin to switch its output from logic low to logic high. As a result, depending on the propagation delays of NOR gate G1 and the inverter driving transistor P2, the EQ pulse may turn on transistor N1 slightly before transistor P2 is turned off. Ideally, in order to avoid charge loss and reduction in the power efficiency of the pump, charge-sharing between clock signals X1 and X2 should occur when both buffers B1 and B2 are in an inactive state.